By the time we inherited the project, one thing that had never been done was an end-to-end check of system latency, probably in part because ADC sampling in the original design was so non-deterministic that it couldn’t be measured if anyone tried. When we got the ADC locked on a hardware timer, sample windows were spaced with minimal jitter, and the results were bereft of most of the prior high-frequency trash created by the sampling method itself.
The previous firm had done poor lowpass filtering of the ADC input as well, so it fell to us to do some digital lowpass filtering — which introduces a phase delay of its own. So when we got the system right side up, we had two things to analyze and measure: Latency introduced by the time required to complete the ADC conversion itself plus phase shift of a moving average FIR digital lowpass filter.
At left is a representation of the (noisy) input signal at top and the filtered and delayed (by 520 microseconds) output at bottom. Critically, the wave shape is undistorted, indicating that at least at the frequencies of interest, sampling is happening on repeatable intervals.